Electronic circuits that make use of scaled matching of internal electronic components are common. For example, digital-to-analog converters are well known in the art. These devices take an input digital word and output an analog value corresponding to the magnitude of the digital input word. The current-steering type of DAC provides its analog output as a current value. Thus, as typically configured, a small magnitude digital input word results in a small output current and a large magnitude digital input word results in a correspondingly large output current. Current steering DACs are useful in a plethora of applications, particularly any type of application where digital control is used and an analog output is required. For example, emerging standards for communications systems require DACs with sample rates in the hundreds of millions of samples per second and resolutions of 10-14 bits or more. The sample rate is simply the number of times per unit time period that the DAC looks at a new input and generates a new output. The resolution refers to the size in bits of the digital input word. A one-bit resolution would correspond to only two possible output states. A 14-bit resolution corresponds to 214 (16384) output states.
In a 14-bit converter, for example, the current produced by the largest bit must be 8192 times larger than the current produced by the smallest bit, with an accuracy better than half the size of the smallest bit (i.e. the fractional error in the largest bit must be less than 1 part in 16384). Due at least in part to mismatch between current-source transistors, it is typically very difficult to fabricate physical circuits with such resulting accuracy. Accordingly, it is common to utilize a mechanism for trimming or tuning the DAC after its fabrication so that the current-source transistors behave nearly ideally after trimming. In the past, such trimming mechanisms have included, for example, laser-trimmable components, such as cermet or nichrome resistors. Large transistors have also been used to try to minimize mismatch. Such approaches are usually undesirable because they increase the die area used by the DAC. Moreover, trimmable resistor components are usually undesirable because they take relatively large amounts of die area and require special processing steps not compatible with system-on-chip (SOC) integration. Randomized layouts have also been used, as have architectures where plural transistors are used for each current steering element in order to average out performance differences among nearly identical transistors. Such intrinsic matching approaches generally require complicated layout techniques that usually result in a substantial adverse impact on die size and chip yield. Electrical trimming with on-chip capacitors has been used but requires continuous calibration of the current sources in the DAC because the calibration information held in the capacitors is continuously degrading due to leakage currents. Continuous calibration approaches are undesirable in general because they suffer from the effects of switching noise and require complicated circuitry to adjust current sources on the fly without impacting the performance of the DAC.
Electrically-trimmable DACs typically use thermometer-decoded current sources, largely because trimming identical current sources against a fixed reference current is much easier than trimming binary-weighted current sources. However, trimming an N-bit thermometer-decoded DAC requires 2N trim steps. Alternatively, a binary-weighted DAC requires only N trim steps, but a more complicated trimming procedure requiring accurate scaling of either the current reference or the trimmed current.
Existing trim procedures for binary-weighted DACs are typically “bottom-up”, meaning that first the second significant bit (2sb) magnitude is trimmed to twice the least-significant bit (LSB) magnitude, then the 3sb is trimmed to twice the 2sb magnitude, then the 4sb is trimmed to twice the 3sb magnitude, etc. Bottom-up trimming is attractive because doubling (or otherwise scaling) a bit's magnitude requires the simple operations of either analog addition or analog multiplication, but has the potential drawback that small errors in a bit are doubled at each trim step, necessitating a large trim range. In a “top-down” trim, first the (N−1)th significant bit magnitude would be made equal to half the Nsb magnitude, then the (N−2)th significant bit magnitude would be made equal to half the (N−1)th bit magnitude, etc. Top-down trim would be attractive because trim errors are halved at each trim step, reducing the required trim range, however, the apparent requirement for halving a bit's magnitude by means of the relatively difficult operation of analog division presents a significant drawback to its implementation.